Current state of the art in the system-level design of Systems on a Chip. The focus is in the hardware, scheduling, and applications at the highest levels of design.
The combination of single-chip transistor desnity, size, and power constraints, and the end of an era of steady growth of performance for single core processors has led to the era of Systems on a Chip in which multiple cores cooperate to carry out some computing goal. Currently, the questions outpace the solutions in this area of research, even though there is a body of research that has begun on Systems on a Chip and multi-core computing in the past decade. This course is structured to ehlp students understand the state of the art of Systems on a Chip design and, in so doing, prepare them to critically evaluate future research as it develops over the next decades.
Percentage of Course
|1. Applications - emerging trends in contrast to specifications and benchmark suites||20%|
|2. Architectures - networks on chip and multi-core organization||20%|
|3. Design - the impact of simulation and modeling||20%|
|4. Evaluation - performance as speed (latency and throughput), power, size and other||20%|
|5. Trends Justification - numerical quantification of and written justification of the impact of changes in relationships between Applications, Architectures, Design and Evaluation||20%|