VLSI & Design Automation | ECE | Virginia Tech


VLSI & Design Automation

Cell-based, VLSI design the most widely used approach in system-on-a-chip design relies on a building-block infrastructure with standard cell libraries. All aspects of VLSI benefit from standard cell libraries, including full custom design, automatic layout generation, physical design, logic synthesis, CAD tools, and testing.

Computer render of the VT cell library

Virginia Tech's cell libraries for VLSI design have been used by more than 280 universities worldwide.

An ECE research team, led by Dong Ha, has been developing and distributing a standard-cell library targeting the TSMC-0.25um, 2.5-volt CMOS process available via MOSIS, along with CAD tools for testing and the source code. The library has been used by more than 280 universities worldwide.

The team VTVT (Virginia Tech for VLSI Telecommunications) group recently has been awarded a $421,337 grant (subject to renewal for three years) from the NSF for further development of the library.

"Commercial library cells are the supplier's proprietary information, and understandably, suppliers usually impose certain restrictions on the access and use of their library cells," said Dong Ha, VTVT director. "Those restrictions on commercial library cells severely hamper academic VLSI research and teaching activities. This grant aims to address the problem so that academic researchers can freely exchange designs utilizing those library cells."

Planned improvements include development of library cells for other processing technologies; development of RAM and ROM compilers and data converters; and provision of additional features and simulation libraries.

Researchers from the FERMAT (Formal Engineering Research with Models, Abstraction, and Transformation) laboratory are working with an MIT-startup firm, Bluespec, Inc., to extend the features of the firm's Electronic Design Automation tools.

Bluespec's toolset, which is based on functional programming technology, delivers a high-level design and verification environment to current Verilog and VHDL designers of ASICs and FPGAs.

Gaurav Singh, a FERMAT Ph.D. student is working to develop low-power features for Bluespec's hardware compiler, and Hiren Patel, also a Ph.D. student, is helping Bluespec develop extensions that would enable SystemC-based designers to apply Bluespec's computation model. FERMAT director, Sandeep Shukla, will also work closely with the firm this summer.

FERMAT researchers have been collaborating with the Los Alamos National Laboratory (LANL) to develop reliability analysis methodologies and tools for reconfigurable nanosystems.

As part of the DOE funded Reconfigurable and Adaptive Systems research project, Paul Graham from LANL's International, Space and Response (ISR) division has been working with ECE's Sandeep Shukla and Ph.D. student Debayan Bhaduri.

The effort has lead to the development of a number of tools, including NANOLAB a tool for designing and analyzing commercial-off-the-shelf nanoscale CMOS systems. Tools for designing and analyzing molecular memories and molecular reconfigurable systems have also been developed.

Bhaduri has also been working with Heather Quinn from the ISR Space Data Systems, on transitioning these tools to the different projects within ISR. Quinn and Bhaduri are developing an improved reliability and performance analysis system called STARS for nanoscale computational structures. STARS integrates seamlessly with the current hardware design flow. These tools are being applied in image and signal processing systems critical for the threat reduction and nonproliferation missions of ISR.

The effort's long-term goal is an unified framework for (1) designing reliable, high performance and power-efficient systems from unreliable nanodevices, and (2) developing computing architectures for novel non-silicon nanodevices such as carbon nanotubes and single electron transistors. Such a framework will help the development of complex nanoscale sensor systems systems that will be very critical in national and homeland security. Further, with the development of the Center for Integrated Nanotechnologies (CINT) jointly between LANL and Sandia National laboratories, such a nanoscale design framework will impact a number of future applications. Further information on this research project is available at LAUR-06-1628

Print Version

image of article

(208KB .pdf) Print Version