We always demand more from our computer systems.
They need to be faster, more adaptable, and more efficient. ECE researchers are using new methods to meet these demands- including letting computers dream.
Intelligent beings must sleep and dream, seemingly against all survival instincts. Dreaming is necessary for efficient mental processes. The human brain uses levels of parallelism well beyond what is achievable using conventional forms of computer parallelism. ECE researchers have demonstrated how a dream-inspired phase of computation can be used to develop parallel contexts, or greatly simplified algorithmic processes tuned to specific usage scenarios, which are then selected for real-time (awake) use. Our goal of this research is to demonstrate how a novel form of scalability, and constant performance over increasing algorithmic complexity, mimics the way the brain is utilized in real-time, and enables the utilization of virtually limitless levels of parallelism.
FPGA Technology
Software Defined Radio
Radio technology is rapidly evolving, and as processing capabilities and algorithms become more complex, the need for alternative compilation and user interface abstraction increases. Field Programmable Gate Array (FPGA) technology introduces unique reconfigurable hardware architectures that can aid in software defined radio (SDR) design. FPGAs have greater processing capability than traditional General Purpose Processors (GPP) found in desktop workstations.
ECE research has been building on an ongoing project, GR-easy, that augments a Linux-based open source SDR development platform, GNU Radio, with FPGA processing capabilities. By delegating processing-intensive portions of a radio design to the Xilinx Zynq FPGA architecture, the domain of deployable radios by GNU Radio is broadened. Xilinx Zynq integrates the FPGA fabric and CPU onto a single chip, eliminating the need for a controlling host computer, thus providing a single, portable, low-power, embedded platform.
Big Data
In today's world of big-data computing, access to massive, complex data sets has reached an unprecedented level, and the task of intelligently processing such data into useful information is a growing concern to the high-performance computing community. However, domain experts, who are the brains behind this processing, typically lack the skills required to build FPGA-based hardware accelerators ideal for their applications. ECE researchers are developing a usable, end-to-end accelerator development methodology that attempts to bridge this gap between domain experts and the vast computational capacity of FPGA-based heterogeneous platforms.
To accomplish this, a development flow was assembled, targeting the Convey Hybrid-Core HC-1 heterogeneous platform and utilizing an existing graphical design environment for design entry. The efficacy of the flow in extending FPGA-based acceleration to non-engineers in the life sciences was informally tested at an NSF-funded summer workshop. A group of five life-science-focused, non-engineer participants made significant modifications to a bare-bones Smith-Waterman accelerator, not only extending its functionality but also improving its performance.
