ECE 4530 Hardware-Software Codesign | ECE | Virginia Tech

Description

An introduction to the design of mixed hardware-software systems, focusing on common underlying modeling concepts, the design of hardware-software interfaces, and the trade-offs between hardware and software components. Students will use simulation tools to conduct experiments with mixed hardware-software systems in the area of embedded systems.

Why take this course?

In classic embedded system design, hardware and software components are developed independently by separate design teams. This leads to a slow and inefficient design process. There is general agreement in the design community that a combined consideration of hardware and software design issues will lead to more efficient systems and a more efficient design process. This course, targeted at computer engineers, addresses these issues.The course provides an introduction in hardware-software co-design. It outlines the basic strengths of hardware and software implementations, and shows how to combine those into a successful system design. The focus is on the commonalities in the design process of hardware and software, as well as on the design of hardware-software interfaces.

Prerequisites

C- or better in 2534, 3504 or 3544.

The course assumes a basic knowledge of microprocessor system design, including assembly and C programming, basic processor architecture, interrupts, memory-buses, and peripherals, as covered in ECE 3534. The course assumes a basic knowledge of custom hardware design, including the design of synchronous sequential circuits, hardware arithmetic, and hardware controllers, as covered in ECE 3504.

• analyze and explain the control-flow and data-flow of a software program and a cycle-based hardware description,
• transform simple software programs into cycle-based hardware descriptions with equivalent behavior and vice versa,
• partition simple software programs into hardware and software components, and create appropriate hardware-software interfaces to reflect this partitioning,
• identify performance bottlenecks in a given hardware-software architecture and optimize them by transformations on hardware and software components, and
• use simulation software to co-simulate software programs with cycle-based hardware descriptions.